Linux and Computer Acronyms
This table provides a set of commonly used acronyms during Linux developent.
| ACE | Advanced Cryptography Engine VIA Nehemiah core processor integrate a cryptography engine that can encrypt or decrypt data at a sustained rate of 12.8 Gb/s. |
| ATA | AT Attachment Interface This standard describes a technique to connect disk drives to the mainboard and perform I/O with them. |
| ATAPI | AT Attachment with Packet Interface Extension This standard specifies the AT Attachment Interface between host systems and storage devices. It provides a common attachment interface for systems manufacturers, systems integrators, and suppliers of intelligent storage devices. |
| BPT | Branch Prediction Table This is a small buffer inside a modern (RISC) CPU. This is the simplest dynamic method to predict whether a conditional branch is taken or not. This helps speed up the execution of a computer program on a modern CPU. It is a simple array, indexed by the lower portion of the address of the instruction. The memory contains one bit that says whether a branch is taken or not. As an improvement, todays CPUs often contain a two bit memory per address, so that one falsely predicted branch doesn't disturb the pattern. |
| BTB | Branch Target Buffer This is a small cache inside of a modern (RISC) CPU that caches the destination address of a (conditional) branch command. This way the CPU does not need to calculate the destination address but can fetch the proper command right after decoding the current command, and does not have to wait until the destination address is calculated. |
| BTS | Branch Target Stack This is an optional processing resource which is used to accelerate indirect branches, such as subroutine returns. The BTS is managed by software, and in processors which implement it, can provide the branch target address in place of the general register specified in the branch instruction. PA-RISC 2.0 implements this, for example. |
| CISC | Complex Instruction Set Computer This is a computer designed after the paradigm "provide a command for every task, make programming simple". As a result the ISA contains a very large set of valid obcodes, and often certain tasks can be performed by more than one list of commands and each command requires a fair amount of time for execution. The 80x86 architecture is an example. |
| CMP | Chip Multi-Processing This is poor-mans multiprocessing on Power4 processors, called hyperthreading on x86 compatible ones and multithreading on Sparc processors. See SMT. |
| CPU | Central Processing Unit The main part of a computer, its 'brain', consisting of the central memory, arithmetic logic unit and control unit. It is also called the central processor. |
| CSA | Comprehensive System Accounting This framework provides methods for collecting per-process resource usage data, monitoring disk usage, and charging fees to specific login accounts. CSA provides features which are not available with the other Linux accounting packages. |
| DMA | Direct Memory Access This is a method used by many computer devices such as sound cards and I/O adaptes to transfer data directly to and from memory, which represents a fast way of transfer. There are only few DMA channels in a computer system. |
| ECN | Explicit Congestion Notification Explicit Congestion Notification (ECN) allows routers to notify clients about network congestion, resulting in fewer dropped packets and increased network performance. However, on the Internet, there are many broken firewalls which refuse connections from ECN-enabled machines, and it may be a while before these firewalls are fixed. |
| IPMI | Intelligent Platform Management Interface This standard for system management provides ways to detect managed devices in the system and sensors attached to them. |
| ISA | Instruction Set Architecture This is the portion of the CPU which is visible to the programmer or compiler writer. It consists of the number and type of registers, the set of valid object codes (obcodes), methods to access the memory and the way control flow is managed. It is often referenced as the list of valid obcodes like ADD, ADDF etc. |
| LDT | Local Descriptor Table The LDT is a per-process memory management table used by the x86 processor. It defines all of the segments which are used in Intel 486 chip. The local descriptor tables contain entries associated with a given process. |
| LRO | Large Receive Offload A system to speed up network packet reception. See |
| LSM | Linux Security Modules The Linux Security Modules project provides a lightweight, general purpose framework for access control. Contemporary computing environments are increasingly hostile. Adding enhanced access control models to the kernel improves host security and can help a server survive malicious attacks. Security research has provided many types of enhanced access controls effective for different environments. The LSM framework allows access control models to be implemented as loadable kernel modules. |
| LTT | Linux Trace Toolkit It is possible for the kernel to log important events to a trace facility. Doing so, enables the use of the generated traces in order to reconstruct the dynamic behavior of the kernel, and hence the whole system. |
| MTD | Memory Technology Device Memory Technology Devices are flash, RAM and similar chips, often used for solid state file systems on embedded devices. Hardware drivers do not need to know anything about the storage formats used, such as FTL, FFS2, etc., but will only need to provide simple routines for read, write and erase. |
| MTRR | Memory Type Range Register On Intel P6 family processors (Pentium Pro, Pentium II and later) these registers may be used to control processor access to memory ranges. This is most useful when you have a video (VGA) card on a PCI or AGP bus. Enabling write-combining allows bus write transfers to be combined into a larger transfer before bursting over the PCI/AGP bus. This can increase performance of image write operations 2.5 times or more. |
| MTU | Maximum Transmission Unit This is the maximum size of a packet that can be transfered through the given medium, often ethernet. For example, ethernet often has an MTU of 1500, thus packets have to be splitted into that size. |
| NCQ | Native Command Queuing Modern hard disks are able to reorder the stream of commands that are received in order to become more efficient. This is a new form of TCQ for SATA (Serial ATA) disks. |
| NIC | Network Interface Card/Chip This is simply the physical network interface, like the ethernet card of the token ring card or whatever. |
| RISC | Reduced Instruction Set Computer This is a computer designed after the paradigm "provide only basic techniques and let the programmer combine them for high-level tasks". As a result the ISA contains only a small set of valid obcodes. In order to fulfil a certain task the programmer needs to combine several CPU commands and by properly sorting them can gain benefits from the way the CPU processes them, hence much better optimization. RISC architectures are not used for the mass market unfortunately, examples would be PowerPC, MIPS, PA-RISC, ARM etc. |
| RNG | Random Number Generator A system that generates pseudo-random numbers, the more random, the better. This refers to /dev/random on Linux. |
| SMT | Simultaneous Multithreading This is poor-mans multiprocessing on single CPUs. One physical processor able to switch its processing context (including program counter, registers and the like) and hence acts like several different logical (or virtual) processors. See also CMP. |
| TCQ | Tagged Command Queueing This is an optional feature in the SCSI-2 and ATA specification that allows a drive to accept multiple I/O requests for later execution. A tag is added to the command so the drive and the operating system can keep track of them. The drive will probably reorder the requests to optimize seeks. |
| TLB | Translation Lookaside Buffer This is a small cache inside a modern (RISC) CPU. It caches the last address translations from virtual addresses to physical addresses. It is indexed by a portion of the virtual address and the value contains the physikcal page number, protection field, valid bit and often a dirty bit. It is used as remedy to access the entire translation table (which can be quite large and contain multiple steps) for each memory access in a modern CPU. |
| TSC | Time Stamp Counter On a Pentium, an internal 64 bit register is incremented at every CPU internal clockcycle. Hence, you are able to get the number of clock cycles since the CPU was powered up or reset. Determining the difference between two polls of the CPU for the number of clock cycles is a very effective way to time your code. |
| TSO | TCP Segmentation Offload This is a technique that makes use of special features of the NIC. When large packets are to be sent through the network, splitting them into smaller packets is offloaded to the NIC hardware. This reduces load of the CPU and is thus a performance gain when the NIC supports this. |
| TSS | Task State Segment In the kernel, for each process. |
Some of these abbreviations and many more explanations are found
with the dict command.